1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) apparatus for demodulating pulse signals having an information carrying pulse of a constant pulse width such as PPM (pulse-phase- or pulse-position-modulated) signals.
2. Description of Background Art
PPM called pulse-phase-modulation or pulse-position-modulation has been extensively used in the field of optical communication utilizing infrared rays or the like. The PPM is a manner to transmit information according to a pulse position of an information pulse in each cycle of a pulse signal having a certain period. Generally, for convenience, 4-PPM, 16-PPM and the like are preferably used.
FIGS. 11A and 11B show a basic concept of the PPM. FIG. 11A shows a modulation waveform on 4-PPM, and FIG. 11B a modulation waveform on 16-PPM. In this specification, it is assumed that a bit of a signal takes on one of two logical values "0" and "1". Herein, taking an example of a 4-PPM modulation system shown in FIG. 11A, explanation will be given in detail. According to the 4-PPM modulation system, information is transmitted by 2 bits, not by 1 bit. Conceivable combinations of 2 bit information are four kinds of "00", "01", "10", and "11". In these four kinds, phases or positions in which pulses exist are different. The information pulse exists in any of the four positions called pulse slots provided by dividing one period of the pulse signal into four parts. In the 16-PPM shown in FIG. 11B, one period of the pulse signal is divided into 16 parts and 16 pulse slots are obtained.
FIG. 12 shows a constitution for demodulating the PPM modulation waveform. The PPM demodulating apparatus comprises a PLL part 1 and a PPM demodulation part 2. The PLL part 1 takes out timing necessary for demodulation from a received PPM signal and gives it to the PPM demodulation part 2 as a reproduction clock signal.
In the PPM demodulation part 2, there are following methods practiced in general: an integration discharge filter method for comparing voltages between respective pulse slots by integration and carrying out integration assuming that the pulse exists in the pulse slot which shows a maximum value; a maximum voltage detection method for simply performing a sampling at a certain spot in each pulse slot to detect the pulse slot which shows a maximum value, instead of carrying out the integration. However, in case of carrying out demodulation by using these methods, a reproduction clock signal having a relatively high precision to the pulse slot is required. The PLL part 1 generates the reproduction clock signal necessary for reproduction in the PPM demodulation part 2. With respect to realization of the PLL part 1, there is a system which includes an analog circuit only, a system which includes a digital circuit only, a system which includes a mixture of an analog circuit and a digital circuit, and the like, of which the system which includes the digital circuit only is the easiest circuit to realize. In case of realizing the PLL part 1 with the digital circuit only, the part 1 has a phase comparison part 3 and a counter part 4. A prior art digital system PLL circuit is disclosed, for example, in Japanese Unexamined Utility Model Publication JP-U 62-109528 (1987).
FIGS. 13A through 13C show operational principles in case the PLL part 1 of FIG. 12 is realized by a digital circuit. A PLL motion clock is provided by an external part of the PPM demodulating apparatus. FIG. 13A shows a condition in which a PPM signal to be received and a change in counter value of the counter part 4 match in phase with each other. When the counter value of the counter part 4 is sampled on the rising edge of the PPM signal, it is shown as exactly zero, and this condition is to be called "matching in phase" between the PPM signal and the counter value. The phase comparison part 3 of FIG. 12 inspects whether the PPM signal and the counter value match in phase with each other.
The phase comparison part 3 does not exercise any control when the two phases match with each other, but in case they do not match, it gives a correction signal to the counter part 4 so as to bring the phases to matching. FIG. 13B shows how the counter part 4 is corrected in case the counter value is delayed against the PPM signal, and FIG. 13C shows how it is corrected in case the counter value is advanced. In other words, in these examples the counter part 4 continues to count up unless it is given the correction signal by the phase comparison part 3. In case the counter value is delayed against the PPM signal, counting up is made only once for two parts, and on the contrary in case the counter part 4 is advanced, the counting up is stopped only once. By exercising such control, the phase of the counter is to be made to match with the PPM signal at all times.
On the other hand, the reproduction clock signal is formed from an output of the counter part 4. In FIGS. 13A through 13C, a most significant bit of the counter value is the reproduction clock signal. For this reason, the reproduction clock signal rises when the counter value changes from 3 to 4, and it falls when the value changes from 7 to 0. As the control is made so that the PPM signal and the counter value match in phase with each other at all times, in an example shown in FIGS. 13A through 13C, a phase relationship in which the reproduction clock signal rises in a vicinity of a middle point of the pulse of the PPM signal, is obtained.
In a conventional PPM demodulating apparatus shown in FIG. 12, in case of realizing the PLL part 1 with a digital circuit, as shown in FIGS. 13A through 13C, the PLL motion clock having a high frequency in comparison with inputted PPM signal is required. First, when a pulse width of a pulse to be used for PPM is represented as To(s), a frequency of a clock signal in which a time of the pulse width is one period becomes 1/To (Hz). Assuming this frequency to be fo (Hz), it can be seen that the PLL part requires a PLL motion clock having the frequency of n.times.f.sub.o (Hz), wherein n shows a number of times for the counter part 4 to count up per pulse slot time. In the examples shown in FIGS. 13A through 13C, n=8. This n is to be referred to simply as "a precision of PLL" hereafter. Further, "PLL with a precision of n" may be defined as "a PLL circuit whose motion clock is a clock having a 1/n of pulse width time of the pulse used for PPM as one period."
The larger a value of the PLL precision n, the more "delicate" phase adjustment becomes possible. Especially, in case of using the aforesaid integration discharge filter method or maximum voltage detection method in the PPM demodulation part 2, there is a possibility even for a slight phase shift to affect performance to a great degree. Therefore, it is necessary to make the value of the PLL precision n large so as to perform delicate phase adjustment.
Also, there is an advantage that the performance against noise can be improved as the value of the precision n is increased. It is possible that various types of noise are mixed into a PPM signal shown in FIG. 12 in a process of communications. If noise is inputted while the counter value indicates an amount other than 0, the phase comparison part 3 corrects the counter value 4 based on the noise, resulting in a shift in the phase of the reproduction clock signal. Though the phase shift caused by the erroneous correction is to be amended when a next pulse of the PPM signal is received, in case the noise is further inputted before the receipt of the next PPM pulse, there is a possibility for the phase shift to spread rapidly. As an amount of the phase to be erroneously corrected on receipt of one noise pulse becomes 2.pi./n, it is seen that the PLL having the larger value of precision n is less susceptible to an effect of the phase shift against the noise.
As PPM demodulation systems, there are ones in which a sampling per se necessitates a highly precise alignment, such as the above-mentioned integration discharge filter method and maximum voltage detection-method, and ones which do not necessitate so highly precise an alignment. The systems which do not necessitate so highly precise an alignment includes one in which the PPM signal converted to a digital level is sampled by the reproduction clock signal, and it is assumed that a signal existed in the pulse slot showing a sampling result was 1. However, even in such the system, in order to obtain improvement in the noise resistance performance, it is necessary to make the value of the PPL precision n large.
According to the conventional PPM demodulating apparatus, for reasons as stated above, the value of the precision n is made large and kept for example at 8 or more. However, the larger the value of n, the higher electric power consumption of the circuit. In general, in the electronic circuit, when operation is repeated at a high speed, an increase in the power consumption is inevitable due to a change of state. Particularly, in case of constituting a circuit by C-MOS, compared with little power consumption in static operation, the power consumption sharply increases as the frequency of the motion becomes higher.
Assuming a case of carrying out a communication of for example 2 Mbps by 16-PPM, the pulse width becomes 125 ns, and the value of the frequency in which the pulse width is one period becomes fo=8 MHz. Accordingly, when the precision is n.gtoreq.8, the motion clock of PLL is 64 MHz or more. Assuming that a device is equipped with such a PPM demodulating apparatus to obtain a motion clock based on a master clock, the device requires a master clock of 64 MHz or more. At present, however, there is a large possibility for the master clock to be lower than 64 MHz, and it is difficult to equip the device having such a low master clock with a PPM demodulating apparatus having a PLL motion clock of 64 MHz or more. Namely, in the conventional digital system PPM demodulation apparatus, because of necessity to make the value of the PLL precision n large under a requirement for the demodulation system and a requirement for the noise resistance performance, there are problems of not only an increase in power consumption but also an increased possibility that the PLL motion clock is not obtained in equipment provided with the PPM demodulating apparatus.
The prior art of Japanese Unexamined Utility Model Publication JP-U 62-109528 (1987) discloses an concept that the frequency of the motion clock necessary for obtaining the reproduction clock signal which falls within the same frequency fluctuation range as heretofore can be reduced to 1/2. However, the prior art can merely reduce the conventional precision n of 8 to 4.